VCSEL Technology for Next Generation 3D Sensing Applications — Part 1

By Sabbir Rangwala

A view from the US space shuttle Endeavour shows the right solar array deployed, 03 December 2000, from the newly installed P-6 truss assembly (L) on the International Space Station. Space walkers US Carlos Noriega and US Joe Tanner installed truss.
  1. The supply chain is able to conclusively demonstrate the ability to deliver these requirements (operational capability)
Figure 2: IbeoNext LiDAR (Left), VCSEL and SPAD Array (Right)
  1. Back-side illuminated VCSELs: allow for more uniform current distribution leading to higher VCSEL power and lifetimes. This requires a shift to 940 nm wavelengths and back-illuminated VCSELs.
  2. 3D integration of optical and electronic wafers: via flip chip or other interconnect platforms would provide wafer level packaging, and reduce device size, which is critical for consumer applications like smart phones and smart glasses (Ibeo also counts among its investors, AAC Technologies in China, which provides a variety of acoustic, haptic and optical sensors into these applications).
Figure 3: Point Cloud Data at 200 m Range (10% reflectivity, 100 kLux ambient light), Center 45°x13° Region
Figure 4: Industrial, Augmented Reality and Consumer Applications for VCSEL based ToF LiDAR-PMD Technologies
  1. Higher speed operation: the ability to operate the VCSEL at higher speeds is important for dynamic scenes and safety applications
  2. VCSEL Addressability: current interconnect schemes make it impractical to operate the VCSEL to support adaptive, ROI imaging. Next generation VCSELs need to address this.
  3. Green Fabrication: GaAs substrate based processes are not compatible with recycling processes. Currently, regulatory bodies accommodate this constraint, although this is liable to change in the future.
  4. Wafer level integration of VCSEL and driver electronics: traditional opto-electronics relies on discrete integration of the optical and electronic semiconductors. Wafer level integration in a CMOS environment would help reduce costs, and lead to smaller devices
  5. Chip scale LiDAR: Ideally, if wafer level integration were possible, one could envision a complete LiDAR system on a chip which is critical from a size and integration perspective.

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